K7A203600A sram equivalent, 64kx36-bit synchronous pipelined burst sram.
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-.
GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each b.
The K7A203600A is a 2,359,296-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 64K words of 36bits and integrates address and control registers, a 2-.
Image gallery
Download